1. Field of Invention
This invention relates to integrated circuit (IC) fabrication, and particularly to a pitch-halving IC process and an IC structure made by the same process.
2. Description of Related Art
The resolution in a photolithography process depends on the wavelength of the exposure light, the numerical aperture (NA) of the optical system and the design of the photomask, and has a certain limit according to the exposure conditions. When the resolution required by an array of patterns exceeds the resolution of the lithographic system, for example, in a case of forming the gate line array of a high-density memory like a DRAM of next generation, a pitch reduction method is needed, mainly based on the spacer forming technique.
For example, patterns of dense conductive lines beyond lithographic resolution can be formed as follows. Parallel base line patterns are lithographically defined and trimmed, linear spacers having a smaller width/pitch and a double number are formed on the sidewalls of the base line patterns, and then the base line patterns are removed, leaving the linear spacers as the target line patterns beyond the lithographic resolution.
However, the contact pads of such small-pitch conductive lines are difficult to form at the line ends, due to their larger width for sufficient electrical contact.